The present invention relates to a timing extracting circuit for extracting the timing for discriminating data in an optical receiver in a high-speed optical communication system and, more particularly, to a timing extracting circuit for controlling the phase of a clock signal so that the phase relationship between the clock signal which indicates the timing for discriminating data and a data signal becomes optimal, and a phase detector for detecting the phase difference between the data signal and the clock signal.
The optical receiver in a high-speed optical communication system converts a data signal of which waveform is distorted during transmission or a data signal carrying noise into a shaped digital signal, in other words, executes what is called data reproduction. In such data reproduction, the optical receiver extracts a clock signal out of a received data signal, and reproduces the shaped data signal by using the extracted clock signal. One of the problem in data reproduction is that the margin for discriminating the data signal is very small due to such distortion or noise. It is therefore necessary to control the phase relationship between the data signal input to a data discriminating portion and an extracted clock signal which indicates the timing for discriminating the data signal so that it is accurately optimal. In addition, it is necessary that the phases relationship between the data signal and the clock signal does not shift. For example, it is necessary to control the phase relationship so that the clock signal for discriminating the data signal rises at the center of the data signal.
FIG. 20 shows an example of the structure of an optical receiver used in an optical communication system. The reference numeral 1 represents an optoelectric conversion circuit for converting an input optical signal (digital signal) into an electric signal, 2 a high-frequency amplifier for amplifying a data signal of, for example, 10 Gbps which is output form the optoelectric conversion circuit 1, 3 a timing extracting circuit for extracting a clock signal having the same frequency as the bit rate of the data signal from the data signal received, 4 an equalizing circuit for executing the equalization control of the data signal, and 5 a discriminating circuit for discriminating the data signal by using the clock signal which is output from the timing extracting circuit 3.
In such an optical receiver, it is necessary to keep the phase relationship between the data signal and the clock signal input to the discriminating circuit 5 optimal. FIG. 21 is an explanatory view of the relationship between a data signal and a clock signal. The symbol DATA represents a data signal and CLOCK a clock signal. When the data D0, D1, . . . are established on the signal line, the clock signal CLOCK should be generated at the center of the data D0, D1, . . . so as to fetch them. In this manner, accurate data discriminating/reproducing operation is enabled.
In the actual system, however, the characteristic of each circuit subtly changes due to the change of the ambient temperature or the fluctuation of the supply voltage, so that the phase relationship between the data signal and the clock signal slips from the optimal state, thereby making the accurate discrimination impossible. Especially, the higher the speed of the data signal to be processed is, the shorter the time slot (the period of one data) becomes, and only a slight change in the phase is apt to make the accurate discrimination impossible.
To solve this problem, some circuits have been proposed which detect the phase relationship between the data signal and the clock signal and control the phase of the clock signal so that the optimal phase relationship is kept. FIG. 22 shows an automatic phase control circuit using two D flip flops (D-FFs) and two exclusive OR gates (EXOR circuits) (IEEE Transaction on Electron Devices VOL. ED-32, No.12 December 1985 "A Self Correcting Clock Recovery Circuit", Hogge, pp. 2704-2706). In FIG. 22, the symbols U1, U4 denote D flip flops (D-FFs) each provided with a clock input terminal (C) to which a first signal is input, a data input terminal (D) to which a second signal is input, and output terminals (Q, *Q) for outputting stored logical values. The D-FF stores and outputs the logical value of the second signal (input of the D) in the instant of the rising edge of the first signal (input of the C) and stores the logical value until the time of the rising edge of the next first signal. The symbols U2, U3 denote EXOR circuits for executing the exclusive OR operation of the input of the D and the output of the Q of the U1 and U4, respectively. The symbol U5 represents a comparator for comparing the average values (the output of a low-pass filter having an R-C structure) of the output signals of the U2 and U3 and outputting a voltage signal corresponding to the difference therebetween, U6 a voltage controlled oscillator for outputting the clock signal CLOCK having a frequency corresponding to the difference signal, and U7 a gate for outputting the non-inverting signal and the inverting signal of the clock signal CLOCK.
When the phase difference between the clock signals of the two D flip flops (D-FFs) U1, U4 are .pi., the input and output signals a, b, c of the U1, U4 have the waveforms shown in FIG. 23. The U2, U3 (EXOR circuits) detect the phase information of the input/output signals a, b and b, c of the U1 and U4, respectively, and input the average values of the detection signals d and e to the comparator U5 via the low-pass filter. The comparator U5 outputs the difference between the average values of the detection signals d and e, and the voltage controlled oscillator U6 outputs a clock signal having a frequency and a phase corresponding to the difference. The gate U7 inputs the clock signal to the CLOCK input terminal (C terminal) of the U1 (D-FF) and inputs the inverting signal of the clock signal to the CLOCK input terminal (C terminal) of the U4 (D-FF). Thereafter, the same operation is repeated on the basis of a new clock signal. Owing to such feedback control, the two inputs of the comparator U5, i.e., the outputs of the U2 (EXOR circuit) and U3 (EXOR circuit) are made equal. At this time, a clock signal is generated at the center of the data signal. In FIG. 23, although a clock signal g is generated at the center of the data signal a, the phase of the clock signal g lags or leads the center of the data signal in the beginning. Such a phase lead/phase lag of the clock signal g reduces/increases the pulse width of the output signal of the U2 (EXOR circuit). In contrast, the pulse width of the output signal of the U3 (EXOR circuit) is constant irrespective of a phase lead/phase lag. Consequently, the comparator U5 outputs a difference signal which corresponds to a phase lead/phase lag. However, by the above-described feedback control, the outputs of the U2 (EXOR circuit) and U3 (EXOR circuit) finally become equal, and the clock signal g is generated at the center of the data signal.
When the phase relationship between the data signal a and the clock signal b is optimal, the pulse width of the output of the EXOR circuit is the half of the time slot. This means that the EXOR circuit U2, U3 are required to have an operation speed approximate to the bit rate of the data signal. However, when the phase of a clock signal leads that of the data signal as in the case of pulling, the pulse width of the output of the EXOR circuit becomes narrower. For this reason, the EXOR circuit is required to operate at a higher speed, so that it may fair well be that, especially, a system in which the device does not have a sufficiently high-speed capacity causes a trouble in operation.
FIG. 24 shows the structure of a timing extracting circuit for solving the problem in the conventional circuit shown in FIG. 22. In FIG. 24, the reference numeral 4 represents an equalizing circuit, and 5 a discriminating circuit having a D flip flop (D-FF) 5a. By inputting a data signal to the DATA input terminal D of the flip flop 5a and a clock signal CLOCK to the CLOCK input terminal, the D-FF latches the data signal at the rising edge of the clock signal and holds the state until the next rising edge. In the timing extracting circuit 3, the reference numeral 3a represents a phase detector for outputting a voltage signal which corresponds to the phase difference between the clock signal CLOCK and the data signal DATA, 3b a voltage controlled oscillator (VCO) for oscillating at a frequency corresponding to the input voltage, and 3c a delaying portion for delaying the clock phase by 180.degree.. The output of the delaying portion 3c is input to the C terminal of the first flip flop 5a as a clock signal. In the phase detector 3, the reference numeral 3a-1 represents a D flip flop (D-FF), and 3a-2 a low-pass filter (LPF). The clock signal CLOCK output from the voltage controlled oscillator 3b is input to the DATA input terminal (D terminal) of the D flip flop (D-FF) 3a-1, and the data signal DATA is input to the CLOCK input terminal (C terminal). The output of the D flip flop (D-FF) 3a-1 is averaged by the low-pass filter 3a-2 and then input to the voltage controlled oscillator 3b.
The D-FF 3a-1 stores and outputs the logical value ("1" or "0") of the signal (clock signal CLOCK) input to the DATA input terminal (D terminal) at the rising edge of the signal (data signal DATA) input to the CLOCK input terminal (C terminal), and holds the logical value until the time of the rising edge of the next data signal. Accordingly, when the phase of the clock signal CLOCK lags that of the data signal DATA, as shown in FIG. 25(1), the D-FF 3a-1 outputs a signal D-FF OUT of a low level (=E.sub.L). On the other hand, when the phase of the clock signal CLOCK leads that of the data signal DATA, as shown in FIG. 25(2), the D-FF 3a-1 outputs a signal D-FF OUT of a high level (=E.sub.H).
As a result, the low-pass filter 3a-2 outputs a voltage signal which is proportional to the phase difference between the clock signal CLOCK and the data signal DATA, and the voltage controlled oscillator 3b oscillates at a frequency corresponding to the voltage signal so that the phase difference becomes zero. The above-described feedback control is thereafter executed, and the phases of the clock signal and the data signal coincide with each other. The delaying portion 3c delays the phase of the clock signal CLOCK by 180.degree. and outputs a clock signal CLOCK which rises at the center of the data signal DATA. Consequently, the discriminating circuit 5 can discriminate the data signal at the center thereof where the margin for discriminating the data signal is the largest. That is, it is possible to make the phase relationship between the data signal DATA and the clock signal CLOCK optimal.
In the phase detector 3a shown in FIG. 24, the rising edge of the data signal DATA is only used for the latch control of the D-FF 3a-1. This method has no problem when the timing at which the data signal rises agrees with the timing at which the data signal trails (when the duty of the data signal is 100%). However, when there is difference in timing (when the duty is not 100%), it is impossible to generate a clock signal CLOCK at the center of the data signal DATA, so that the discriminating circuit 5 cannot discriminate the data signal at the center of the data signal DATA. This state is shown in FIGS. 26A and 26B. The phase detector 3a controls the phase of the clock signal so that the rising edge of the data signal DATA agrees with the rising edge of the clock signal CLOCK. As a result, if the duty of the data signal is 100%, the clock signal CLK which is delayed by 180.degree. from the rising edge of the data signal rises at the center of the data signal DATA, as shown in FIG. 26A. On the other hand, when the duty is less than 100%, the clock signal CLK which is delayed by 180.degree. from the rising edge of the data signal rises not at the center of the data signal DATA but at the position moved from the center by the amount corresponding to the difference between the current duty and 100%, as shown in FIG. 26B.
FIG. 27 shows the structure of a conventional timing extracting circuit for solving the problem in the circuit shown in FIG. 24. The same reference numerals are provided for the elements which are the same as those shown in FIG. 24. In the timing extracting circuit 3, the reference numeral 3a denotes a first phase detector for outputting a voltage signal which corresponds to a phase difference between a clock signal CLOCK and a data signal DATA, 3d a second phase detector for outputting a voltage signal which corresponds to a phase difference between the clock signal CLOCK and the inverting signal *DATA of a data signal DATA, 3e a phase control circuit for controlling the phase of the input clock signal CLOCK IN and outputting a clock signal CLOCK, 3f a differential amplifier for inputting a voltage signal which corresponds to the difference between the output signals of the first and second phase detectors 3a and 3d, 3g an inverting gate for inverting an input data signal DATA IN, and 3c a delaying portion for delaying the clock phase by 180.degree.. The output of the delaying portion 3c is input to the discriminating circuit 5 as a clock signal CLK.
In the phase detector 3a, the reference numeral 3a-1 represents a D flip flop (D-FF), and 3a-2 a low-pass filter. The clock signal CLOCK output from the phase control circuit 3e is input to the DATA input terminal (D terminal) of the D flip flop (D-FF) 3a-1, and the data signal DATA is input to the CLOCK input terminal (C terminal). The output of the D flip flop 3a-1 (D-FF) is averaged by the low-pass filter 3a-2 and then input to the non-inverting input terminal of the differential amplifier 3f. In the phase detector 3d, the reference numeral 3d-1 represents a D flip flop (D-FF), and 3d-2 a low-pass filter. The clock signal CLOCK output from the phase control circuit 3e is input to the DATA input terminal (D terminal) of the D flip flop (D-FF) 3d-1, and the inverting data signal *DATA which is obtained by inverting the data signal is input to the CLOCK input terminal (C terminal). The output *Q of the D flip flop 3d-1 (D-FF) is averaged by the low-pass filter 3d-2 and then input to the inverting input terminal of the differential amplifier 3f. The symbol * represents the inversion of a logical value ("1", "0).
The timing extracting circuit 3 shown in FIG. 27 has an additional D-FF as compared with the timing extracting circuit 3 shown in FIG. 24, so that it is possible to detect the phase relationship between the data signal and the clock signal not only at the rising edge of the data signal but also at the falling edge of the data signal, and deal with a change in the duty of the data signal by averaging the outputs of the two phase detectors 3a and 3d. More specifically, the clock phase is detected at both the rising edge and the falling edge, and the phase control circuit 3e controls the phase of the clock signal so that the output Q of the phase detector 3a and the inverted output (output *Q) of the phase detector 3d are equal. As a result, when the phase of the clock signal CLOCK is delayed by 180.degree. by the delaying portion 3c, a clock signal CLK is generated at the center of the data signal.
According to the timing extracting circuit shown in FIG. 27, even if the duty varies, it is possible to generate a clock signal at the center of the data signal. In such a timing extracting circuit, however, since a D-FF is added to the structure of the timing extracting circuit shown in FIG. 24, the circuitry scale becomes larger. In addition, since two phase detectors are required, the phase adjustment between the two phase detectors is disadvantageously necessary.